SIPUS SIPUS SIPUS SIPUS SIPUS SIPUS CPU 1212c SIPUS PLC

De Pacto CPU 1212C habet:

• III fabrica versions cum alia potentia copia et imperium voltages.
• Integrated virtutis copia aut ut late-range AC vel DC potentia Supple (LXXXV ... CCLXIV V ac XXIV V DC)
• Integrated XXIV V encoder / onus current copia:
  Nam recta nexu sensoriis et encoders. In CCC ma output current etiam pro usu ut onus potentia copia.
• VIII Integrated Digital Inits XXIV V DC (Current Meners / Sources input (IEC Type I Current Meners)).
• VI integrated digital outputs, aut XXIV V DC vel Nullam.
• II Integrated Analog Inputs 0 ... X V.
• II pulsus outputs (PTO) cum frequency usque ad C khz.
• Pulsum, latitudo modulatae outputs (PWM) cum frequency usque ad C khz.
• Integrated ethernet interface (TCP / IP patria, ISO-on-TCP).
• 4 fast counters (3 with max. 100 kHz; 1 with max. 30 kHz), with parameterizable enable and reset inputs, can be used simultaneously as up and down counters with 2 separate inputs or for connecting incremental encoders.
• Expansion additional communicationis interfaces, eg Rs485 aut Rs232.
• Expansion by Analog aut Digital signals directe in CPU per signum Board (cum retention of CPU ascendens dimensiones).
• Expansion per amplis Analog et digital input et output signo per signum modules.
• Optio memoria expansion (Simaticae Memoria Card).
• PID controller cum Auto-tuning functionality.
• Integralis realis-vicis horologium.
• Interrupt inputs:
  Nam maxime ieiunium responsio ad ortum vel cadit marginibus processus annuit.
• Removibilibus terminals in omnibus modules.
• Simulator (libitum):
  Nam simulantes integrated inputs et temptationis in user progressio.